The present invention relates to a compound semiconductor switching circuit device, and specifically, relates to a compound semiconductor switching circuit device with insertion loss reduced.
Mobile communication equipment such as cellular phones often uses microwaves in the GHz range and includes switching devices to switch high frequency signals in circuits to switch antennas, transmitting and receiving, and the like in many cases. For the switching devices, a field-effect transistor (hereinafter, referred to as an FET) using gallium arsenide (GaAs) is used in many cases because the mobile communication equipment deals with high frequencies. Accordingly, a monolithic microwave integrated circuit (MMIC) in which the above switching circuits are integrated is being developed.
FIG. 9A shows a principle circuit diagram of a compound semiconductor switching circuit device which is called a single pole double throw (SPDT) and uses GaAs FETs.
In this compound semiconductor switching circuit device, sources (or drains) of a first FET FET1 and a second FET FET2 are connected to a common input terminal IN, and gates of the FETs 1 and 2 are connected to first and second control terminals Ctl1 and Ctl2 through resistors R1 and R2, respectively. Moreover, drains (sources) of the FET1 and FET2 are connected to first and second output terminals OUT1 and OUT2, respectively.
Signals applied to the first and second control terminals Ctl1 and Ctl2 are complementary signals. One of the FETs to which an H level signal is applied is turned on and transmits to one of the output terminals a high frequency analog signal inputted to the input terminal IN. The resistors R1 and R2 are disposed for the purpose of preventing the high frequency signal from leaking through the gate electrodes to DC potential of the first and second control terminals Ctl1 and Ctl2, which are AC grounded. In logic of this switching circuit, for transmitting a signal to the first output terminal OUT1, for example, 3V is applied to the first control terminal Ctl1, which is closer to the first output terminal OUT1, and 0V is applied to the second control terminal Ctl2. On the contrary, for transmitting a signal to the second output terminal OUT2, a bias signal of 3V is applied to the second control terminal Ctl2, which is closer to the second output terminal OUT2, and a bias signal of 0V is applied to the first control terminal Ctl1.
However, in some requests from users, it is necessary to build reverse logic. Specifically, in such a reverse logic, as shown in FIG. 9B, for transmitting a signal to the first output terminal OUT1, for example, 3V is applied to the first control terminal Ctl1, which is more distant from the first output terminal OUT1, and 0V is applied to the second control terminal Ctl2. On the contrary, for transmitting a signal to the second output terminal OUT2, a bias signal of 3V is applied to the second control terminal Ctl2, which is more distant from the second output terminal OUT2, and a bias signal of 0V is applied to the first control terminal Ctl1. Hereinafter, the switching circuit device having the above reverse logic is referred to as a reverse control type switching circuit device.
FIG. 10 shows an example of a compound semiconductor chip in which the switching circuit of FIG. 9B is integrated.
The FET1 and FET2 for switching are disposed in the center of a GaAs substrate. The gate electrodes of the FET1 and FET2 are connected to the resistors R1 and R2, respectively. In the periphery of the substrate, pads I, O1, O2, C1, and C2, which serve as the common input terminal IN, first and second output terminals OUT1 and OUT2, and first and second control terminals Ctl1 and Ctl2, respectively, are provided around the FET1 and FET2. Wires indicated by dotted lines are formed of a gate metal layer (Ti/Pt/Au) 220 simultaneously with the formation of gate electrodes 217 of the FETs, and wires indicated by solid lines are formed of a pad metal layer (Tl/Pt/Au) 230 which connects the elements to each other and forms the pads. The pad metal layer 230 forms source electrodes 215 and drain electrodes 216, as a second metal layer of each electrode, and the like. Under the pad metal layer 230, source electrodes and drain electrodes, as a first metal layer of each electrode, and the like are formed of an ohmic metal layer (AuGe/Ni/Au), which are overlapped by the pad metal layer and therefore is not shown in FIG. 10.
The gate electrodes of the FET1 are connected to the first control terminal pad C1, which is more distant from the FET1, through the resistor R1. The gate electrodes of the FET2 are connected to the second control terminal pad C2, which is more distant from the FET2, through the resistor R2. The resistors R1 and R2 are disposed under a pad wiring 330 with a nitride film interposed therebetween. The pad wiring 330 is formed of the pad metal layer 230 and extended from the common input terminal pad I. The technology is described for instance in the Japanese Patent Application publication No. 2002-368164.
As described above, in the reverse control type switching circuit device, it is necessary to connect the first and second control terminal pads C1 and C2 to the gate electrodes of the FET1 and FET2, which are located at farther positions, by extending the resistors R1 and R2 in the chip. At this time, the resistors R1 and R2 are disposed between the common input terminal pad I and the FET1 and FET2 to prevent an increase in chip area due to extending of the resistors R1 and R2.
FIG. 11 is a cross-sectional view along a line i-i of FIG. 10.
As shown in the drawing, the resistors R1 and R2 between the common input terminal pad I and the FET1 and FET2 are doped regions obtained by doping, for example, a high concentration n type impurity into a substrate 211. On the surface of the substrate 211, a nitride film 260 is provided over the resistors R1 and R2, and on the nitride film 260, the pad metal layer 230 forming the common input terminal pad I is extended to provide the pad wiring 330. The pad wiring 330 is extended to the FET1 and FET2 and forms the source and drain electrodes as the second metal layer of each electrode. Under and around the common input terminal pad I, a high concentration peripheral impurity region 350 is provided to increase isolation.
The high frequency analog signal inputted to the common input terminal IN of the switching circuit device is transmitted in the pad wiring 30 and reaches the source (or drain) electrodes of the FET1 and FET2. At this time, however, there is a problem that part of the high frequency signal transmitted in the pad wiring 30 leaks through the nitride film 260 to the resistors R1 and R2 under the nitride film 260.
The resistors R1 and R2 are connected to the first and second control terminal pads C1 and C2, respectively. That is, when the high frequency signal leaks to the resistors R1 and R2, the high frequency signal reaches the control terminals, each of which is at GND potential at high frequencies, thus increasing an insertion loss between the common input terminal IN and the first output terminal OUT1 (or second output terminal OUT2) of the switching circuit device.